(1) Field of the Invention
The invention relates to the general field of liquid crystal displays, more particularly to the problem of providing a high aperture ratio without an increase in the complexity of the associated manufacturing process.
(2) Description of the Prior Art
FIG. 1 shows a schematic diagram of the circuit used to control a plurality of individual pixels, each comprising a Liquid Crystal (LC) device, arranged as an X-Y addressable array.
A layer of LC 1 is located between two electrodes, at least one of which is transparent. One of said electrodes is grounded and the other electrode is connected to one of the scan lines 2 and to one of the data lines 3, thus making it uniquely addressable--it will not be activated unless voltage is applied to both the appropriate scan and data lines simultaneously. Power to drive the LC is supplied by the data line but its availability is controlled from the scan line through Field Effect Transistor (FET) 5.
Additionally, a capacitor 4 is included with each pixel for the purpose of extending the time that the pixel is active beyond the very short time during which it receives voltage from both the scan and data lines simultaneously. This is analogous to using a long persistent phosphor in a cathode ray tube.
The physical implementation of the circuit diagrammed in FIG. 1 forms the subject matter of the present invention. Problems that must be overcome in order to achieve a good implementation include improving the aperture ratio of the device, eliminating or reducing places where shorting may occur between different parts of the structure, and providing a cost effective process for its manufacture.
A conventional implementation, typical of the prior art, is shown in FIGS. 2(a) and (b), the former being a cross-section of the latter through AA. LC 15 is sandwiched between two glass substrates. In addition to Thin Film Transistor (TFT) 16, storage capacitor 11 has been located at the same level as scan (or gate) line 14 to increase the opening of aperture 12. Capacitor layer 11 and black matrix layer 13 combine to block out extraneous light. This structure has to allow for extra space to avoid the possibility of side-to-side shorting between capacitor 11 and scan line 14, since they are at the same level. This goes counter to the requirement that space be limited in order to increase pixel density (i.e. keep the pixel pitch small) so only a limited aperture ratio can be achieved with this structure.
FIG. 3(a) shows, in schematic cross-section, an example of an improved approach to the problem that has been described in the prior art by Takahashi et al. (`A high-aperture-ratio pixel structure for high-density a-Si TFT liquid crystal light valves` by N. Takahashi et al. the SID 93 digest pp. 610-613). In this structure, LC 15 is contained between upper and lower glass plates 23 and 27 respectively. The gate electrode 20 and the storage capacitor 21 are located at different levels. Light shields 21 are separated from FET control gate 20 by insulating layer 24, the space beween the light shields defining device aperture 25. This determines the amount of light that is allowed to pass through transparent electrode 26. This design requires the presence of a second light shield 22 that is located on upper glass plate 23. FIG. 3(b) is a plan view of the structure of FIG. 3(a).
This structure allows more latitude in determining the size of aperture 25 (in FIG. 3(a)) but it requires additional process steps relative to other known structures and, in particular, it requires the presence of the secondary light shield 22 in order to avoid illumination of the TFT. Continuing our reference to FIG. 3(a), scan line 20 and transparent pixel electrode 26 are located on the same side as common electrode 21, so the common electrode of storage capacitor 21 cannot be fully utilized to block the electric field of the scan line. This causes some light leakage 30 (in FIG. 3(c)) in one corner of the aperture, requiring light shield 21 to have larger area.
Other prior art that relates to this area includes U.S. Pat. No. 5,028,122 (July 1991) by Hamada et al. which describes overlapping the gate electrodes with the pixel electrodes so as to provide additional capacitance. This is not the problem solved by the present invention.